642 lines
25 KiB
C
642 lines
25 KiB
C
/*
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*
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* JAGUAR.H Hardware Equates for JAGUAR System
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*
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* COPYRIGHT 1992-1994 Atari Computer Corporation
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* UNAUTHORIZED REPRODUCTION, ADAPTATION, DISTRIBUTION,
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* PERFORMANCE OR DISPLAY OF THIS COMPUTER PROGRAM OR
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* THE ASSOCIATED AUDIOVISUAL WORK IS STRICTLY PROHIBITED.
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* ALL RIGHTS RESERVED.
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*
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* Last Modified: 11/03/2016 - toarnold
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*/
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#include <stdint.h>
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#ifndef _jagcore_h
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#define _jagcore_h 1
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/* Custom data types */
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typedef volatile uint16_t vuint16_t;
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typedef volatile uint32_t vuint32_t;
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typedef volatile uint64_t vuint64_t;
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/* GENERIC DEFINES */
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#define DRAM 0x000000 /* Physical Start of RAM */
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#define USERRAM 0x004000 /* Start of Available RAM */
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#define ENDRAM 0x200000 /* End of RAM */
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#define INITSTACK (ENDRAM-4) /* Recommended Stack Location */
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/*
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* CPU REGISTERS
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*/
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#define V_AUTO (vuint32_t *)0x100 /* 68000 Level 0 Autovector */
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/*
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* Masks for INT1 CPU Interrupt Control
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*/
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#define C_VIDENA 0x0001 /* Enable CPU Video Interrupts */
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#define C_GPUENA 0x0002 /* Enable CPU GPU Interrupts */
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#define C_OPENA 0x0004 /* Enable CPU OP Interrupts */
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#define C_PITENA 0x0008 /* Enable CPU PIT Interrupts */
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#define C_JERENA 0x0010 /* Enable CPU Jerry Interrupts */
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#define C_VIDCLR 0x0100 /* Clear CPU Video Interrupts */
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#define C_GPUCLR 0x0200 /* Clear CPU GPU Interrupts */
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#define C_OPCLR 0x0400 /* Clear CPU OP Interrupts */
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#define C_PITCLR 0x0800 /* Clear CPU PIT Interrupts */
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#define C_JERCLR 0x1000 /* Clear CPU Jerry Interrupts */
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/*
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* JAGUAR REGISTERS
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*/
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#define BASE 0xF00000 /* TOM Internal Register Base */
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/*
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* TOM REGISTERS
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*/
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#define HC (vuint16_t *)(BASE+4) /* Horizontal Count */
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#define VC (vuint16_t *)(BASE+6) /* Vertical Count */
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#define LPH (vuint16_t *)(BASE+8) /* Horizontal Lightpen */
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#define LPV (vuint16_t *)(BASE+0x0A) /* Vertical Lightpen */
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#define OB0 (vuint16_t *)(BASE+0x10) /* Current Object Phrase */
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#define OB1 (vuint16_t *)(BASE+0x12)
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#define OB2 (vuint16_t *)(BASE+0x14)
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#define OB3 (vuint16_t *)(BASE+0x16)
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#define OLP (vuint32_t *)(BASE+0x20) /* Object List Pointer */
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#define OBF (vuint16_t *)(BASE+0x26) /* Object Processor Flag */
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#define VMODE (vuint16_t *)(BASE+0x28) /* Video Mode */
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#define BORD1 (vuint16_t *)(BASE+0x2A) /* Border Color (Red & Green) */
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#define BORD2 (vuint16_t *)(BASE+0x2C) /* Border Color (Blue) */
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#define HDB1 (vuint16_t *)(BASE+0x38) /* Horizontal Display Begin One */
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#define HDB2 (vuint16_t *)(BASE+0x3A) /* Horizontal Display Begin Two */
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#define HDE (vuint16_t *)(BASE+0x3C) /* Horizontal Display End */
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#define VS (vuint16_t *)(BASE+0x44) /* Vertical Sync */
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#define VDB (vuint16_t *)(BASE+0x46) /* Vertical Display Begin */
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#define VDE (vuint16_t *)(BASE+0x48) /* Vertical Display End */
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#define VI (vuint16_t *)(BASE+0x4E) /* Vertical Interrupt */
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#define PIT0 (vuint16_t *)(BASE+0x50) /* Programmable Interrupt Timer (Lo) */
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#define PIT1 (vuint16_t *)(BASE+0x52) /* Programmable Interrupt Timer (Hi) */
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#define BG (vuint16_t *)(BASE+0x58) /* Background Color */
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#define INT1 (vuint16_t *)(BASE+0xE0) /* CPU Interrupt Control Register */
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#define INT2 (vuint16_t *)(BASE+0xE2) /* CPU Interrupt Resume Register */
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#define CLUT (vuint16_t *)(BASE+0x400) /* Color Lookup Table */
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#define LBUFA (vuint32_t *)(BASE+0x800) /* Line Buffer A */
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#define LBUFB (vuint32_t *)(BASE+0x1000) /* Line Buffer B */
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#define LBUFC (vuint32_t *)(BASE+0x1800) /* Line Buffer Current */
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/*
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* OBJECT PROCESSOR EQUATES
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*/
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#define BITOBJ 0 /* Bitmap Object Type */
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#define SCBITOBJ 1 /* Scaled Bitmap Object Type */
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#define GPUOBJ 2 /* GPU Interrupt Object Type */
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#define BRANCHOBJ 3 /* Branch Object Type */
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#define STOPOBJ 4 /* Stop Object Type */
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#define O_REFLECT 0x00002000 /* OR with top LONG of BITMAP object */
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#define O_RMW 0x00004000
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#define O_TRANS 0x00008000
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#define O_RELEASE 0x00010000
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#define O_DEPTH1 (0<<12) /* DEPTH Field for BITMAP objects */
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#define O_DEPTH2 (1<<12)
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#define O_DEPTH4 (2<<12)
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#define O_DEPTH8 (3<<12)
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#define O_DEPTH16 (4<<12)
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#define O_DEPTH32 (5<<12)
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#define O_NOGAP (1<<15) /* Phrase GAP between image phrases */
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#define O_1GAP (2<<15)
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#define O_2GAP (3<<15)
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#define O_3GAP (4<<15)
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#define O_4GAP (5<<15)
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#define O_5GAP (6<<15)
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#define O_6GAP (7<<15)
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#define O_BREQ (0<<14) /* CC field of BRANCH objects */
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#define O_BRGT (1<<14)
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#define O_BRLT (2<<14)
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#define O_BROP (3<<14)
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#define O_BRHALF (4<<14)
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#define O_STOPINTS 0x00000008 /* Enable Interrupts in STOP object */
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/*
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* VIDEO INITIALIZATION CONSTANTS
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*/
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#define NTSC_WIDTH 1409 /* Width of screen in clocks */
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#define NTSC_HMID 823 /* Middle of screen in clocks */
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#define NTSC_HEIGHT 241 /* Height of screen in pixels */
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#define NTSC_VMID 266 /* Middle of screen in half-lines */
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#define PAL_WIDTH 1381 /* Same as above for PAL */
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#define PAL_HMID 843
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#define PAL_HEIGHT 287
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#define PAL_VMID 322
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/* The following mask will extract the PAL/NTSC flag bit from the */
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/* CONFIG register. NTSC = Bit Set, PAL = Bit Clear */
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#define VIDTYPE 0x10
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/* The following are Video Mode Regiter Masks */
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#define VIDEN 0x0001 /* Enable Video Interrupts */
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#define CRY16 0x0000 /* 16-bit CRY mode */
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#define RGB24 0x0002 /* 24-bit RGB mode */
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#define DIRECT16 0x0004 /* 16-bit Direct mode */
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#define RGB16 0x0006 /* 16-bit RGB mode */
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#define GENLOCK 0x0008 /* Not supported on Jaguar Console */
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#define INCEN 0x0010 /* Enable Encrustation */
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#define BINC 0x0020 /* Select Local Border Color */
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#define CSYNC 0x0040 /* Enable Composite Sync */
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#define BGEN 0x0080 /* Clear Line Buffer to BG register */
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#define VARMOD 0x0100 /* Enable Variable Resolution mode */
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#define PWIDTH1 0x0000 /* Pixel Dividers */
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#define PWIDTH2 0x0200
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#define PWIDTH3 0x0400
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#define PWIDTH4 0x0600
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#define PWIDTH5 0x0800
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#define PWIDTH6 0x0A00
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#define PWIDTH7 0x0C00
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#define PWIDTH8 0x0E00
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/*
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* GPU REGISTERS
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*/
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#define G_FLAGS (vuint32_t *)(BASE+0x2100) /* GPU Flags */
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#define G_MTXC (vuint32_t *)(BASE+0x2104) /* GPU Matrix Control */
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#define G_MTXA (vuint32_t *)(BASE+0x2108) /* GPU Matrix Address */
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#define G_END (vuint32_t *)(BASE+0x210C) /* GPU Data Organization */
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#define G_PC (vuint32_t *)(BASE+0x2110) /* GPU Program Counter */
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#define G_CTRL (vuint32_t *)(BASE+0x2114) /* GPU Operation Control/Status */
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#define G_HIDATA (vuint32_t *)(BASE+0x2118) /* GPU Bus Interface high data */
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#define G_REMAIN (vuint32_t *)(BASE+0x211C) /* GPU Division Remainder */
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#define G_DIVCTRL (vuint32_t *)(BASE+0x211C) /* GPU Divider control */
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#define G_RAM (vuint32_t *)(BASE+0x3000) /* GPU Internal RAM */
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#define G_ENDRAM (vuint32_t *)(G_RAM+(4*1024))
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/* GPU Flags Register Equates */
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#define G_CPUENA 0x00000010 /* CPU Interrupt enable bits */
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#define G_DSPENA 0x00000020 /* DSP Interrupt enable bits */
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#define G_PITENA 0x00000040 /* PIT Interrupt enable bits */
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#define G_OPENA 0x00000080 /* Object Processor Interrupt enable bits */
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#define G_BLITENA 0x00000100 /* Blitter Interrupt enable bits */
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#define G_CPUCLR 0x00000200 /* CPU Interrupt clear bits */
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#define G_DSPCLR 0x00000400 /* DSP Interrupt clear bits */
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#define G_PITCLR 0x00000800 /* PIT Interrupt clear bits */
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#define G_OPCLR 0x00001000 /* Object Processor Interrupt clear bits */
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#define G_BLITCLR 0x00002000 /* Blitter Interrupt clear bits */
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/* GPU Control/Status Register */
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#define GPUGO 0x00000001 /* Start and Stop the GPU */
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#define GPUINT0 0x00000004 /* generate a GPU type 0 interrupt */
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#define G_CPULAT 0x00000040 /* Interrupt Latches */
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#define G_DSPLAT 0x00000080
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#define G_PITLAT 0x00000100
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#define G_OPLAT 0x00000200
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#define G_BLITLAT 0x00000400
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/*
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* BLITTER REGISTERS
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*/
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#define A1_BASE (vuint32_t *)(BASE+0x2200) /* A1 Base Address */
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#define A1_FLAGS (vuint32_t *)(BASE+0x2204) /* A1 Control Flags */
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#define A1_CLIP (vuint32_t *)(BASE+0x2208) /* A1 Clipping Size */
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#define A1_PIXEL (vuint32_t *)(BASE+0x220C) /* A1 Pixel Pointer */
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#define A1_STEP (vuint32_t *)(BASE+0x2210) /* A1 Step (Integer Part) */
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#define A1_FSTEP (vuint32_t *)(BASE+0x2214) /* A1 Step (Fractional Part) */
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#define A1_FPIXEL (vuint32_t *)(BASE+0x2218) /* A1 Pixel Pointer (Fractional) */
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#define A1_INC (vuint32_t *)(BASE+0x221C) /* A1 Increment (Integer Part) */
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#define A1_FINC (vuint32_t *)(BASE+0x2220) /* A1 Increment (Fractional Part) */
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#define A2_BASE (vuint32_t *)(BASE+0x2224) /* A2 Base Address */
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#define A2_FLAGS (vuint32_t *)(BASE+0x2228) /* A2 Control Flags */
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#define A2_MASK (vuint32_t *)(BASE+0x222C) /* A2 Address Mask */
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#define A2_PIXEL (vuint32_t *)(BASE+0x2230) /* A2 PIXEL */
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#define A2_STEP (vuint32_t *)(BASE+0x2234) /* A2 Step (Integer) */
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#define B_CMD (vuint32_t *)(BASE+0x2238) /* Command */
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#define B_COUNT (vuint32_t *)(BASE+0x223C) /* Counters */
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#define B_SRCD (vuint64_t *)(BASE+0x2240) /* Source Data */
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#define B_DSTD (vuint64_t *)(BASE+0x2248) /* Destination Data */
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#define B_DSTZ (vuint64_t *)(BASE+0x2250) /* Destination Z */
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#define B_SRCZ1 (vuint64_t *)(BASE+0x2258) /* Source Z (Integer) */
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#define B_SRCZ2 (vuint64_t *)(BASE+0x2260) /* Source Z (Fractional) */
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#define B_PATD (vuint64_t *)(BASE+0x2268) /* Pattern Data */
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#define B_IINC (vuint32_t *)(BASE+0x2270) /* Intensity Increment */
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#define B_ZINC (vuint32_t *)(BASE+0x2274) /* Z Increment */
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#define B_STOP (vuint32_t *)(BASE+0x2278) /* Collision stop control */
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#define B_I3 (vuint32_t *)(BASE+0x227C) /* Blitter Intensity 3 */
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#define B_I2 (vuint32_t *)(BASE+0x2280) /* Blitter Intensity 2 */
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#define B_I1 (vuint32_t *)(BASE+0x2284) /* Blitter Intensity 1 */
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#define B_I0 (vuint32_t *)(BASE+0x2288) /* Blitter Intensity 0 */
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#define B_Z3 (vuint32_t *)(BASE+0x228C) /* Blitter Z 3 */
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#define B_Z2 (vuint32_t *)(BASE+0x2290) /* Blitter Z 2 */
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#define B_Z1 (vuint32_t *)(BASE+0x2294) /* Blitter Z 1 */
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#define B_Z0 (vuint32_t *)(BASE+0x2298) /* Blitter Z 0 */
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/* BLITTER Command Register defines */
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#define SRCEN 0x00000001 /* d00: source data read (inner loop) */
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#define SRCENZ 0x00000002 /* d01: source Z read (inner loop) */
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#define SRCENX 0x00000004 /* d02: source data read (realign) */
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#define DSTEN 0x00000008 /* d03: destination data read (inner loop) */
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#define DSTENZ 0x00000010 /* d04: destination Z read (inner loop) */
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#define DSTWRZ 0x00000020 /* d05: destination Z write (inner loop) */
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#define CLIP_A1 0x00000040 /* d06: A1 clipping enable */
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#define UPDA1F 0x00000100 /* d08: A1 update step fraction */
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#define UPDA1 0x00000200 /* d09: A1 update step */
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#define UPDA2 0x00000400 /* d10: A2 update step */
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#define DSTA2 0x00000800 /* d11: reverse usage of A1 and A2 */
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#define GOURD 0x00001000 /* d12: enable Gouraud shading */
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#define ZBUFF 0x00002000 /* d13: polygon Z data updates */
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#define TOPBEN 0x00004000 /* d14: intensity carry into byte */
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#define TOPNEN 0x00008000 /* d15: intensity carry into nibble */
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#define PATDSEL 0x00010000 /* d16: Select pattern data */
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#define ADDDSEL 0x00020000 /* d17: diagnostic */
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/* d18-d20: Z comparator inhibit */
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#define ZMODELT 0x00040000 /* source < destination */
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#define ZMODEEQ 0x00080000 /* source = destination */
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#define ZMODEGT 0x00100000 /* source > destination */
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/* d21-d24: Logic function control */
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#define LFU_NAN 0x00200000 /* !source & !destination */
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#define LFU_NA 0x00400000 /* !source & destination */
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#define LFU_AN 0x00800000 /* source & !destination */
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#define LFU_A 0x01000000 /* source & destination */
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#define CMPDST 0x02000000 /* d25: pixel compare pattern & dest */
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#define BCOMPEN 0x04000000 /* d26: bit compare write inhibit */
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#define DCOMPEN 0x08000000 /* d27: data compare write inhibit */
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#define BKGWREN 0x10000000 /* d28: data write back */
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#define BUSHI 0x20000000 /* d29 blitter priority */
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#define SRCSHADE 0x40000000 /* d30: shade src data w/IINC value */
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/* The following are ALL 16 possible logical operations of the LFUs */
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#define LFU_ZERO 0x00000000 /* All Zeros */
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#define LFU_NSAND 0x00200000 /* NOT Source AND NOT Destination */
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#define LFU_NSAD 0x00400000 /* NOT Source AND Destination */
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#define LFU_NOTS 0x00600000 /* NOT Source */
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#define LFU_SAND 0x00800000 /* Source AND NOT Destination */
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#define LFU_NOTD 0x00A00000 /* NOT Destination */
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#define LFU_N_SXORD 0x00C00000 /* NOT (Source XOR Destination) */
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#define LFU_NSORND 0x00E00000 /* NOT Source OR NOT Destination */
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#define LFU_SAD 0x01000000 /* Source AND Destination */
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#define LFU_SXORD 0x01200000 /* Source XOR Destination */
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#define LFU_D 0x01400000 /* Destination */
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#define LFU_NSORD 0x01600000 /* NOT Source OR Destination */
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#define LFU_S 0x01800000 /* Source */
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#define LFU_SORND 0x01A00000 /* Source OR NOT Destination */
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#define LFU_SORD 0x01C00000 /* Source OR Destination */
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#define LFU_ONE 0x01E00000 /* All Ones */
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/* These are some common combinations with less boolean names */
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#define LFU_REPLACE 0x01800000 /* Source REPLACEs destination */
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#define LFU_XOR 0x01200000 /* Source XOR with destination */
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#define LFU_CLEAR 0x00000000 /* CLEAR destination */
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/* BLITTER Flags (A1 or A2) register defines */
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/* Pitch d00-d01:
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distance between pixel phrases */
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#define PITCH1 0x00000000 /* 0 phrase gap */
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#define PITCH2 0x00000001 /* 1 phrase gap */
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#define PITCH4 0x00000002 /* 3 phrase gap */
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#define PITCH3 0x00000003 /* 2 phrase gap */
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/* Pixel d03-d05
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bit depth (2^n) */
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#define PIXEL1 0x00000000 /* n = 0 */
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#define PIXEL2 0x00000008 /* n = 1 */
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#define PIXEL4 0x00000010 /* n = 2 */
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#define PIXEL8 0x00000018 /* n = 3 */
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#define PIXEL16 0x00000020 /* n = 4 */
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#define PIXEL32 0x00000028 /* n = 5 */
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/* Z offset d06-d08
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offset from phrase of pixel data from its corresponding
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Z data phrases */
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#define ZOFFS0 0x00000000 /* offset = 0 UNUSED */
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#define ZOFFS1 0x00000040 /* offset = 1 */
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#define ZOFFS2 0x00000080 /* offset = 2 */
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#define ZOFFS3 0x000000C0 /* offset = 3 */
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#define ZOFFS4 0x00000100 /* offset = 4 */
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#define ZOFFS5 0x00000140 /* offset = 5 */
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#define ZOFFS6 0x00000180 /* offset = 6 */
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#define ZOFFS7 0x000001C0 /* offset = 7 UNUSED */
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/* Width d09-d14
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width used for address generation
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This is a 6-bit floating point value in pixels
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4-bit unsigned exponent
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2-bit mantissa with implied 3rd bit of 1 */
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#define WID2 0x00000800 /* 1.00 X 2^1 ( 4<<9) */
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#define WID4 0x00001000 /* 1.00 X 2^2 ( 8<<9) */
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#define WID6 0x00001400 /* 1.10 X 2^2 (10<<9) */
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#define WID8 0x00001800 /* 1.00 x 2^3 (12<<9) */
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#define WID10 0x00001A00 /* 1.01 X 2^3 (13<<9) */
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#define WID12 0x00001C00 /* 1.10 X 2^3 (14<<9) */
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#define WID14 0x00001E00 /* 1.11 X 2^3 (15<<9) */
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#define WID16 0x00002000 /* 1.00 X 2^4 (16<<9) */
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#define WID20 0x00002200 /* 1.01 X 2^4 (17<<9) */
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#define WID24 0x00002400 /* 1.10 X 2^4 (18<<9) */
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#define WID28 0x00002600 /* 1.11 X 2^4 (19<<9) */
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#define WID32 0x00002800 /* 1.00 X 2^5 (20<<9) */
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#define WID40 0x00002A00 /* 1.01 X 2^5 (21<<9) */
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#define WID48 0x00002C00 /* 1.10 X 2^5 (22<<9) */
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#define WID56 0x00002E00 /* 1.11 X 2^5 (23<<9) */
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#define WID64 0x00003000 /* 1.00 X 2^6 (24<<9) */
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#define WID80 0x00003200 /* 1.01 X 2^6 (25<<9) */
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#define WID96 0x00003400 /* 1.10 X 2^6 (26<<9) */
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#define WID112 0x00003600 /* 1.11 X 2^6 (27<<9) */
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#define WID128 0x00003800 /* 1.00 X 2^7 (28<<9) */
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#define WID160 0x00003A00 /* 1.01 X 2^7 (29<<9) */
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#define WID192 0x00003C00 /* 1.10 X 2^7 (30<<9) */
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#define WID224 0x00003E00 /* 1.11 X 2^7 (31<<9) */
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#define WID256 0x00004000 /* 1.00 X 2^8 (32<<9) */
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#define WID320 0x00004200 /* 1.01 X 2^8 (33<<9) */
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#define WID384 0x00004400 /* 1.10 X 2^8 (34<<9) */
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#define WID448 0x00004600 /* 1.11 X 2^8 (35<<9) */
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#define WID512 0x00004800 /* 1.00 X 2^9 (36<<9) */
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#define WID640 0x00004A00 /* 1.01 X 2^9 (37<<9) */
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#define WID768 0x00004C00 /* 1.10 X 2^9 (38<<9) */
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#define WID896 0x00004E00 /* 1.11 X 2^9 (39<<9) */
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#define WID1024 0x00005000 /* 1.00 X 2^10 (40<<9) */
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#define WID1280 0x00005200 /* 1.01 X 2^10 (41<<9) */
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#define WID1536 0x00005400 /* 1.10 X 2^10 (42<<9) */
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#define WID1792 0x00005600 /* 1.11 X 2^10 (43<<9) */
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#define WID2048 0x00005800 /* 1.00 X 2^11 (44<<9) */
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#define WID2560 0x00005A00 /* 1.01 X 2^11 (45<<9) */
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#define WID3072 0x00005C00 /* 1.10 X 2^11 (46<<9) */
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#define WID3584 0x00005E00 /* 1.11 X 2^11 (47<<9) */
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/* X add control d16-d17
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controls the update of the X pointer on each pass
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round the inner loop */
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#define XADDPHR 0x00000000 /* 00 - add phrase width and truncate */
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#define XADDPIX 0x00010000 /* 01 - add pixel size (add 1) */
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#define XADD0 0x00020000 /* 10 - add zero */
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#define XADDINC 0x00030000 /* 11 - add the increment */
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/* Y add control d18
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controls the update of the Y pointer within the inner loop.
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it is overridden by the X add control if they are in add increment */
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#define YADD0 0x00000000 /* 00 - add zero */
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#define YADD1 0x00040000 /* 01 - add 1 */
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/* X sign d19
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add or subtract pixel size if X add control = 01 (XADDPIX) */
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#define XSIGNADD 0x00000000 /* 0 - add pixel size */
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#define XSIGNSUB 0x00080000 /* 1 - subtract pixel size */
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/* Y sign d20
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add or subtract pixel size if Y add control = 01 (YADD1) */
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#define YSIGNADD 0x00000000 /* 0 - add 1 */
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#define YSIGNSUB 0x00100000 /* 1 - sub 1 */
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/*
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* JERRY REGISTERS
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*/
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#define JPIT1 (vuint16_t *)(BASE+0x10000) /* Timer 1 Pre-Scaler */
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#define JPIT2 (vuint16_t *)(BASE+0x10002) /* Timer 1 Divider */
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#define JPIT3 (vuint16_t *)(BASE+0x10004) /* Timer 2 Pre-Scaler */
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#define JPIT4 (vuint16_t *)(BASE+0x10006) /* Timer 2 Divider */
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#define J_INT (vuint16_t *)(BASE+0x10020) /* Jerry Interrupt control (to TOM) */
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#define JOYSTICK (vuint16_t *)(BASE+0x14000) /* Joystick register and mute */
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#define JOYBUTS (vuint16_t *)(BASE+0x14002) /* Joystick register */
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#define CONFIG (vuint16_t *)(BASE+0x14002) /* Also has NTSC/PAL */
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#define MOD_MASK (vuint32_t *)(BASE+0x1A118) /* Mask for ADDQ(SUBQ)MOD */
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#define SCLK (vuint32_t *)(BASE+0x1A150) /* SSI Clock Frequency */
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#define SMODE (vuint32_t *)(BASE+0x1A154) /* SSI Control */
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#define L_I2S (vuint32_t *)(BASE+0x1A148) /* Left I2S Serial */
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#define R_I2S (vuint32_t *)(BASE+0x1A14C) /* Right I2S Serial */
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/*
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* Jerry Interrupt Control Flags
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*/
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#define J_EXTENA 0x0001 /* Enable Jerry External Ints */
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#define J_DSPENA 0x0002 /* Enable Jerry DSP Ints */
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#define J_TIM1ENA 0x0004 /* Enable Jerry Timer 1 Ints */
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#define J_TIM2ENA 0x0008 /* Enable Jerry Timer 2 Ints */
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#define J_ASYNENA 0x0010 /* Enable Jerry Asynch Serial Ints */
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#define J_SYNENA 0x0020 /* Enable Jerry Synch Serial Ints */
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#define J_EXTCLR 0x0100 /* Clear Pending External Ints */
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#define J_DSPCLR 0x0200 /* Clear Pending DSP Ints */
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#define J_TIM1CLR 0x0400 /* Clear Pending Timer 1 Ints */
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#define J_TIM2CLR 0x0800 /* Clear Pending Timer 2 Ints */
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#define J_ASYNCLR 0x1000 /* Clear Pending Asynch Serial Ints */
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#define J_SYNCLR 0x2000 /* Clear Pending Synch Serial Ints */
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/*
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* Joystick Equates
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*
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* Bits when LONGword is formatted as below (from JOYTEST\JT_LOOP.S).
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* Format: xxApxxBx RLDU147* xxCxxxox 2580369#
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*/
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#define JOY_UP 20 /*joypad */
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#define JOY_DOWN 21
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#define JOY_LEFT 22
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#define JOY_RIGHT 23
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#define FIRE_A 29 /*fire buttons */
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#define FIRE_B 25
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#define FIRE_C 13
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#define OPTION 9
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#define PAUSE 28
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#define KEY_STAR 16 /*keypad */
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#define KEY_7 17
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#define KEY_4 18
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#define KEY_1 19
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#define KEY_0 4
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#define KEY_8 5
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#define KEY_5 6
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#define KEY_2 7
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#define KEY_HASH 0
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#define KEY_9 1
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#define KEY_6 2
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#define KEY_3 3
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#define ANY_JOY 0x00F00000 /* AND joyedge with this - joypad was pressed if result is not 0 */
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#define ANY_FIRE 0x32002200 /* AND joyedge with this - A,B C, Option or Pause was pressed if result is not 0 */
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#define ANY_KEY 0x000F00FF /* AND joyedge with this - 123456789*0# was pressed if result is not 0 */
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/*
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* ROM Tables built into Jerry - 128 samples each
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* 16 bit samples sign extended to 32
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*/
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#define ROM_TABLE (int32_t *)(BASE+0x1D000) /* Base of tables */
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#define ROM_TRI (int32_t *)(BASE+0x1D000) /* A triangle wave */
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#define ROM_SINE (int32_t *)(BASE+0x1D200) /* Full amplitude SINE */
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#define ROM_AMSINE (int32_t *)(BASE+0x1D400) /* Linear (?) ramp SINE */
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#define ROM_12W (int32_t *)(BASE+0x1D600) /* SINE(X)+SINE(2*X) : (was ROM_SINE12W) */
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#define ROM_CHIRP16 (int32_t *)(BASE+0x1D800) /* SHORT SWEEP */
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#define ROM_NTRI (int32_t *)(BASE+0x1DA00) /* Triangle w/NOISE */
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#define ROM_DELTA (int32_t *)(BASE+0x1DC00) /* Positive spike */
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#define ROM_NOISE (int32_t *)(BASE+0x1DE00) /* Noise */
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/*
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* JERRY Registers (DSP)
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*/
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#define D_FLAGS (vuint32_t *)(BASE+0x1A100) /* DSP Flags */
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#define D_MTXC (vuint32_t *)(BASE+0x1A104) /* DSP Matrix Control */
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#define D_MTXA (vuint32_t *)(BASE+0x1A108) /* DSP Matrix Address */
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#define D_END (vuint32_t *)(BASE+0x1A10C) /* DSP Data Organization */
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#define D_PC (vuint32_t *)(BASE+0x1A110) /* DSP Program Counter */
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#define D_CTRL (vuint32_t *)(BASE+0x1A114) /* DSP Operation Control/Status */
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#define D_MOD (vuint32_t *)(BASE+0x1A118) /* DSP Modulo Instruction Mask */
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#define D_REMAIN (vuint32_t *)(BASE+0x1A11C) /* DSP Division Remainder */
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#define D_DIVCTRL (vuint32_t *)(BASE+0x1A11C) /* DSP Divider control */
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#define D_MACHI (vuint32_t *)(BASE+0x1A120) /* DSP Hi byte of MAC operations */
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#define D_RAM (vuint32_t *)(BASE+0x1B000) /* DSP Internal RAM */
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#define D_ENDRAM (vuint32_t *)(D_RAM+(8*1024))
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/*
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* JERRY Flag Register Equates
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*/
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#define D_CPUENA 0x00000010 /* CPU Interrupt Enable Bit */
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#define D_I2SENA 0x00000020 /* I2S Interrupt Enable Bit */
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#define D_TIM1ENA 0x00000040 /* Timer 1 Interrupt Enable Bit */
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#define D_TIM2ENA 0x00000080 /* Timer 2 Interrupt Enable Bit */
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#define D_EXT0ENA 0x00000100 /* External Interrupt 0 Enable Bit */
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#define D_EXT1ENA 0x00010000 /* External Interrupt 1 Enable Bit */
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#define D_CPUCLR 0x00000200 /* CPU Interrupt Clear Bit */
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#define D_I2SCLR 0x00000400 /* I2S Interrupt Clear Bit */
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#define D_TIM1CLR 0x00000800 /* Timer 1 Interrupt Clear Bit */
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#define D_TIM2CLR 0x00001000 /* Timer 2 Interrupt Clear Bit */
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#define D_EXT0CLR 0x00002000 /* External Interrupt 0 Clear Bit */
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#define D_EXT1CLR 0x00020000 /* External Interrupt 1 Clear Bit */
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/*
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* JERRY Control/Status Register
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*/
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#define DSPGO 0x00000001 /* Start DSP */
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#define DSPINT0 0x00000004 /* Generate a DSP Interrupt 0 */
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#define D_CPULAT 0x00000040 /* Interrupt Latches */
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#define D_I2SLAT 0x00000080
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#define D_TIM1LAT 0x00000100
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#define D_TIM2LAT 0x00000200
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#define D_EXT1LAT 0x00000400
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#define D_EXT2LAT 0x00010000
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/*
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* JERRY Modulo Instruction Masks
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*/
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#define MODMASK2 0xFFFFFFFE /* 2 byte circular buffer */
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#define MODMASK4 0xFFFFFFFC /* 4 byte circular buffer */
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#define MODMASK8 0xFFFFFFF8 /* 8 byte circular buffer */
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#define MODMASK16 0xFFFFFFF0 /* 16 byte circular buffer */
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#define MODMASK32 0xFFFFFFE0 /* 32 byte circular buffer */
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#define MODMASK64 0xFFFFFFC0 /* 64 byte circular buffer */
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#define MODMASK128 0xFFFFFF80 /* 128 byte circular buffer */
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#define MODMASK256 0xFFFFFF00 /* 256 byte circular buffer */
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#define MODMASK512 0xFFFFFE00 /* 512 byte circular buffer */
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#define MODMASK1K 0xFFFFFC00 /* 1k circular buffer */
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#define MODMASK2K 0xFFFFF800 /* 2k circular buffer */
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#define MODMASK4K 0xFFFFF000 /* 4k circular buffer */
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#define MODMASK8K 0xFFFFE000 /* 8k circular buffer */
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#define MODMASK16K 0xFFFFC000 /* 16k circular buffer */
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#define MODMASK32K 0xFFFF8000 /* 32k circular buffer */
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#define MODMASK64K 0xFFFF0000 /* 64k circular buffer */
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#define MODMASK128K 0xFFFE0000 /* 128k circular buffer */
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#define MODMASK256K 0xFFFC0000 /* 256k circular buffer */
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#define MODMASK512K 0xFFF80000 /* 512k circular buffer */
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#define MODMASK1M 0xFFF00000 /* 1M circular buffer */
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/*
|
|
* SHARED Equates for TOM (GPU) and JERRY (DSP)
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|
*/
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/* Control/Status Registers */
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#define RISCGO 0x00000001 /* Start GPU or DSP */
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#define CPUINT 0x00000002 /* Allow the GPU/DSP to interrupt CPU */
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#define FORCEINT0 0x00000004 /* Cause an INT 0 on GPU or DSP */
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#define SINGLE_STEP 0x00000008 /* Enter SINGLE_STEP mode */
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#define SINGLE_GO 0x00000010 /* Execute one instruction */
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#define REGPAGE 0x00004000 /* Register Bank Select */
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#define DMAEN 0x00008000 /* Enable DMA LOAD and STORE */
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/* Flags Register */
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#define ZERO_FLAG 0x00000001 /* ALU Zero Flag */
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#define CARRY_FLAG 0x00000002 /* ALU Carry Flag */
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#define NEGA_FLAG 0x00000004 /* ALU Negative Flag */
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#define IMASK 0x00000008 /* Interrupt Service Mask */
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/* Matrix Control Register */
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#define MATRIX3 0x00000003 /* use for 3x1 Matrix */
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#define MATRIX4 0x00000004 /* etc... */
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#define MATRIX5 0x00000005
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#define MATRIX6 0x00000006
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#define MATRIX7 0x00000007
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#define MATRIX8 0x00000008
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#define MATRIX9 0x00000009
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#define MATRIX10 0x0000000A
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#define MATRIX11 0x0000000B
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#define MATRIX12 0x0000000C
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#define MATRIX13 0x0000000D
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#define MATRIX14 0x0000000E
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#define MATRIX15 0x0000000F
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#define MATROW 0x00000000 /* Access Matrix by Row */
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#define MATCOL 0x00000010 /* Access Matrix by Column */
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/* Data Organisation Register */
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#define BIG_IO 0x00010001 /* Make I/O Big-Endian */
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|
#define BIG_PIX 0x00020002 /* Access Pixels in Big-Endian */
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#define BIG_INST 0x00040004 /* Fetch Instructions in Big-Endian */
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/* Divide Unit Control */
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#define DIV_OFFSET 0x00000001 /* Divide 16.16 values if set */
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/*******/
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/* EOF */
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/*******/
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#endif
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