596 lines
26 KiB
C
Executable File
596 lines
26 KiB
C
Executable File
/*
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* Copyright (c) 2004 Christiaan Simons <cc_simons@yahoo.com>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef C161U_H
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#define C161U_H
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/*
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v0.3 23/09/04
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Hardware register acces for the Infineon c161u (USB) microcontroller.
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These declarations are to be used with the vbcc(c16x) compiler.
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*/
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#define EPECCLC (*((volatile unsigned int*)0xED00))
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#define EPECID (*((volatile unsigned int*)0xED08))
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#define EPEC_SPTR_IN_R00 (*((volatile unsigned int*)0xED10))
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#define EPEC_SPTR_IN_R01 (*((volatile unsigned int*)0xED12))
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#define EPEC_SPTR_OUT_R00 (*((volatile unsigned int*)0xED14))
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#define EPEC_SPTR_OUT_R01 (*((volatile unsigned int*)0xED16))
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#define EPEC_SPTR_REG10 (*((volatile unsigned int*)0xED18))
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#define EPEC_SPTR_REG11 (*((volatile unsigned int*)0xED1A))
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#define EPEC_SPTR_REG20 (*((volatile unsigned int*)0xED1C))
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#define EPEC_SPTR_REG21 (*((volatile unsigned int*)0xED1E))
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#define EPEC_SPTR_REG30 (*((volatile unsigned int*)0xED20))
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#define EPEC_SPTR_REG31 (*((volatile unsigned int*)0xED22))
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#define EPEC_SPTR_REG40 (*((volatile unsigned int*)0xED24))
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#define EPEC_SPTR_REG41 (*((volatile unsigned int*)0xED26))
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#define EPEC_SPTR_REG50 (*((volatile unsigned int*)0xED28))
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#define EPEC_SPTR_REG51 (*((volatile unsigned int*)0xED2A))
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#define EPEC_SPTR_REG60 (*((volatile unsigned int*)0xED2C))
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#define EPEC_SPTR_REG61 (*((volatile unsigned int*)0xED2E))
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#define EPEC_SPTR_REG70 (*((volatile unsigned int*)0xED30))
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#define EPEC_SPTR_REG71 (*((volatile unsigned int*)0xED32))
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#define EPEC_DPTR_IN_R00 (*((volatile unsigned int*)0xED34))
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#define EPEC_DPTR_IN_R01 (*((volatile unsigned int*)0xED36))
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#define EPEC_DPTR_OUT_R00 (*((volatile unsigned int*)0xED38))
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#define EPEC_DPTR_OUT_R01 (*((volatile unsigned int*)0xED3A))
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#define EPEC_DPTR_REG10 (*((volatile unsigned int*)0xED3C))
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#define EPEC_DPTR_REG11 (*((volatile unsigned int*)0xED3E))
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#define EPEC_DPTR_REG20 (*((volatile unsigned int*)0xED40))
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#define EPEC_DPTR_REG21 (*((volatile unsigned int*)0xED42))
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#define EPEC_DPTR_REG30 (*((volatile unsigned int*)0xED44))
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#define EPEC_DPTR_REG31 (*((volatile unsigned int*)0xED46))
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#define EPEC_DPTR_REG40 (*((volatile unsigned int*)0xED48))
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#define EPEC_DPTR_REG41 (*((volatile unsigned int*)0xED4A))
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#define EPEC_DPTR_REG50 (*((volatile unsigned int*)0xED4C))
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#define EPEC_DPTR_REG51 (*((volatile unsigned int*)0xED4E))
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#define EPEC_DPTR_REG60 (*((volatile unsigned int*)0xED50))
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#define EPEC_DPTR_REG61 (*((volatile unsigned int*)0xED52))
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#define EPEC_DPTR_REG70 (*((volatile unsigned int*)0xED54))
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#define EPEC_DPTR_REG71 (*((volatile unsigned int*)0xED56))
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#define EPEC_CTRL_IN_R0 (*((volatile unsigned int*)0xED58))
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#define EPEC_CTRL_OUT_R0 (*((volatile unsigned int*)0xED5A))
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#define EPEC_CTRL_REG1 (*((volatile unsigned int*)0xED5C))
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#define EPEC_CTRL_REG2 (*((volatile unsigned int*)0xED5E))
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#define EPEC_CTRL_REG3 (*((volatile unsigned int*)0xED60))
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#define EPEC_CTRL_REG4 (*((volatile unsigned int*)0xED62))
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#define EPEC_CTRL_REG5 (*((volatile unsigned int*)0xED64))
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#define EPEC_CTRL_REG6 (*((volatile unsigned int*)0xED66))
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#define EPEC_CTRL_REG7 (*((volatile unsigned int*)0xED68))
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#define EPEC_INT_REG (*((volatile unsigned int*)0xED6A))
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#define EPEC_INTMSK_REG (*((volatile unsigned int*)0xED6C))
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#define USBCLC (*((volatile unsigned int*)0xEE00))
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#define USBD_ID (*((volatile unsigned int*)0xEE08))
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#define USBD_CMD_REG (*((volatile unsigned int*)0xEE10))
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#define USBD_STATUS_REG0 (*((volatile unsigned int*)0xEE12))
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#define USBD_STATUS_REG1 (*((volatile unsigned int*)0xEE14))
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#define USBD_STATUS_REG2 (*((volatile unsigned int*)0xEE16))
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#define USBD_TIME_REG (*((volatile unsigned int*)0xEE24))
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#define USBD_SETUP_REG01 (*((volatile unsigned int*)0xEE26))
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#define USBD_SETUP_REG23 (*((volatile unsigned int*)0xEE28))
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#define USBD_SETUP_REG45 (*((volatile unsigned int*)0xEE2A))
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#define USBD_SETUP_REG67 (*((volatile unsigned int*)0xEE2C))
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#define USBD_TXWR0 (*((volatile unsigned int*)0xEE2E))
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#define USBD_TXEOD0 (*((volatile unsigned int*)0xEE30))
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#define USBD_RXRR0 (*((volatile unsigned int*)0xEE32))
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#define USBD_RX_BYTECNT0 (*((volatile unsigned int*)0xEE34))
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#define USBD_TXWR1 (*((volatile unsigned int*)0xEE36))
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#define USBD_TXEOD1 (*((volatile unsigned int*)0xEE38))
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#define USBD_RXRR1 (*((volatile unsigned int*)0xEE3A))
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#define USBD_RX_BYTECNT1 (*((volatile unsigned int*)0xEE3C))
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#define USBD_TXWR2 (*((volatile unsigned int*)0xEE3E))
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#define USBD_TXEOD2 (*((volatile unsigned int*)0xEE40))
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#define USBD_RXRR2 (*((volatile unsigned int*)0xEE42))
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#define USBD_RX_BYTECNT2 (*((volatile unsigned int*)0xEE44))
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#define USBD_TXWR3 (*((volatile unsigned int*)0xEE46))
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#define USBD_TXEOD3 (*((volatile unsigned int*)0xEE48))
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#define USBD_RXRR3 (*((volatile unsigned int*)0xEE4A))
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#define USBD_RX_BYTECNT3 (*((volatile unsigned int*)0xEE4C))
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#define USBD_TXWR4 (*((volatile unsigned int*)0xEE4E))
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#define USBD_TXEOD4 (*((volatile unsigned int*)0xEE50))
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#define USBD_RXRR4 (*((volatile unsigned int*)0xEE52))
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#define USBD_RX_BYTECNT4 (*((volatile unsigned int*)0xEE54))
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#define USBD_TXWR5 (*((volatile unsigned int*)0xEE56))
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#define USBD_TXEOD5 (*((volatile unsigned int*)0xEE58))
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#define USBD_RXRR5 (*((volatile unsigned int*)0xEE5A))
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#define USBD_RX_BYTECNT5 (*((volatile unsigned int*)0xEE5C))
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#define USBD_TXWR6 (*((volatile unsigned int*)0xEE5E))
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#define USBD_TXEOD6 (*((volatile unsigned int*)0xEE60))
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#define USBD_RXRR6 (*((volatile unsigned int*)0xEE62))
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#define USBD_RX_BYTECNT6 (*((volatile unsigned int*)0xEE64))
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#define USBD_TXWR7 (*((volatile unsigned int*)0xEE66))
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#define USBD_TXEOD7 (*((volatile unsigned int*)0xEE68))
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#define USBD_RXRR7 (*((volatile unsigned int*)0xEE6A))
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#define USBD_RX_BYTECNT7 (*((volatile unsigned int*)0xEE6C))
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#define USBD_CFGVAL (*((volatile unsigned int*)0xEE6E))
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#define USBC_CMD_RESET (*((volatile unsigned int*)0xEE70))
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#define SRCP0 (*((volatile unsigned int*)0xFCE0))
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#define DSTP0 (*((volatile unsigned int*)0xFCE2))
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#define SRCP1 (*((volatile unsigned int*)0xFCE4))
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#define DSTP1 (*((volatile unsigned int*)0xFCE6))
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#define SRCP2 (*((volatile unsigned int*)0xFCE8))
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#define DSTP2 (*((volatile unsigned int*)0xFCEA))
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#define SRCP3 (*((volatile unsigned int*)0xFCEC))
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#define DSTP3 (*((volatile unsigned int*)0xFCEE))
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#define SRCP4 (*((volatile unsigned int*)0xFCF0))
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#define DSTP4 (*((volatile unsigned int*)0xFCF2))
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#define SRCP5 (*((volatile unsigned int*)0xFCF4))
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#define DSTP5 (*((volatile unsigned int*)0xFCF6))
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#define SRCP6 (*((volatile unsigned int*)0xFCF8))
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#define DSTP6 (*((volatile unsigned int*)0xFCFA))
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#define SRCP7 (*((volatile unsigned int*)0xFCFC))
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#define DSTP7 (*((volatile unsigned int*)0xFCFE))
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__esfr(0x0A) volatile unsigned int XADRS1;
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__esfr(0x0B) volatile unsigned int XADRS2;
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__esfr(0x0C) volatile unsigned int XADRS3;
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__esfr(0x0D) volatile unsigned int XADRS4;
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__esfr(0x0E) volatile unsigned int XADRS5;
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__esfr(0x0F) volatile unsigned int XADRS6;
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__esfr(0x12) volatile unsigned int XPERCON;
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__esfrbit(0x12,0x05) volatile __bit XPER5;
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__esfrbit(0x12,0x06) volatile __bit XPER6;
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__esfrbit(0x12,0x07) volatile __bit XPER7;
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__esfr(0x3B) volatile unsigned int IDMEM2;
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__esfr(0x3C) volatile unsigned int IDPROG;
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__esfr(0x3D) volatile unsigned int IDMEM;
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__esfr(0x3E) volatile unsigned int IDCHIP;
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__esfr(0x3F) volatile unsigned int IDMANUF;
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__esfr(0x58) volatile unsigned int SSCTB;
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__esfr(0x59) volatile unsigned int SSCRB;
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__esfr(0x5A) volatile unsigned int SSCBR;
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__esfr(0x5B) volatile unsigned int SSCCLC;
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__esfrbit(0x5B,0x00) volatile __bit SSCDISR;
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__esfrbit(0x5B,0x01) volatile __bit SSCDISS;
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__esfrbit(0x5B,0x02) volatile __bit SSCSUSPEN;
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__esfrbit(0x5B,0x03) volatile __bit SSCEXDISR;
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__esfr(0x60) volatile unsigned int SCUSLC;
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__esfr(0x61) volatile unsigned int SCUSLS;
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__esfr(0x66) volatile unsigned int RTCRELL;
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__esfr(0x67) volatile unsigned int RTCRELH;
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__esfr(0x68) volatile unsigned int T14REL;
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__esfr(0x69) volatile unsigned int T14;
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__esfr(0x6A) volatile unsigned int RTCL;
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__esfr(0x6B) volatile unsigned int RTCH;
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__esfr(0x6C) volatile unsigned int DTIDR;
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__esfr(0x80) volatile unsigned int DP0L;
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__esfr(0x81) volatile unsigned int DP0H;
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__esfr(0x82) volatile unsigned int DP1L;
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__esfr(0x83) volatile unsigned int DP1H;
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__esfr(0x84) volatile unsigned int RP0H;
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__esfr(0x8A) volatile unsigned int XBCON1;
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__esfr(0x8B) volatile unsigned int XBCON2;
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__esfr(0x8C) volatile unsigned int XBCON3;
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__esfr(0x8D) volatile unsigned int XBCON4;
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__esfr(0x8E) volatile unsigned int XBCON5;
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__esfr(0x8F) volatile unsigned int XBCON6;
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__esfr(0xB0) volatile unsigned int UTD3IC;
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__esfrbit(0xB0,0x06) volatile __bit UTD3IE;
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__esfrbit(0xB0,0x07) volatile __bit UTD3IR;
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__esfr(0xB1) volatile unsigned int UTD4IC;
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__esfrbit(0xB1,0x06) volatile __bit UTD4IE;
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__esfrbit(0xB1,0x07) volatile __bit UTD4IR;
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__esfr(0xB2) volatile unsigned int UTD5IC;
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__esfrbit(0xB2,0x06) volatile __bit UTD5IE;
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__esfrbit(0xB2,0x07) volatile __bit UTD5IR;
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__esfr(0xB3) volatile unsigned int UTD6IC;
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__esfrbit(0xB3,0x06) volatile __bit UTD6IE;
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__esfrbit(0xB3,0x07) volatile __bit UTD6IR;
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__esfr(0xB4) volatile unsigned int UTD7IC;
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__esfrbit(0xB4,0x06) volatile __bit UTD7IE;
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__esfrbit(0xB4,0x07) volatile __bit UTD7IR;
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__esfr(0xB5) volatile unsigned int URXRIC;
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__esfrbit(0xB5,0x06) volatile __bit URXRIE;
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__esfrbit(0xB5,0x07) volatile __bit URXRIR;
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__esfr(0xB6) volatile unsigned int UTXRIC;
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__esfrbit(0xB6,0x06) volatile __bit UTXRIE;
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__esfrbit(0xB6,0x07) volatile __bit UTXRIR;
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__esfr(0xB7) volatile unsigned int UCFGVIC;
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__esfrbit(0xB7,0x06) volatile __bit UCFGVIE;
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__esfrbit(0xB7,0x07) volatile __bit UCFGVIR;
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__esfr(0xB8) volatile unsigned int USOFIC;
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__esfrbit(0xB8,0x06) volatile __bit USOFIE;
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__esfrbit(0xB8,0x07) volatile __bit USOFIR;
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__esfr(0xB9) volatile unsigned int USSOIC;
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__esfrbit(0xB9,0x06) volatile __bit USSOIE;
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__esfrbit(0xB9,0x07) volatile __bit USSOIR;
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__esfr(0xBA) volatile unsigned int USSIC;
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__esfrbit(0xBA,0x06) volatile __bit USSIE;
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__esfrbit(0xBA,0x07) volatile __bit USSIR;
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__esfr(0xBB) volatile unsigned int ULCDIC;
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__esfrbit(0xBB,0x06) volatile __bit ULCDIE;
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__esfrbit(0xBB,0x07) volatile __bit ULCDIR;
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__esfr(0xBC) volatile unsigned int USETIC;
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__esfrbit(0xBC,0x06) volatile __bit USETIE;
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__esfrbit(0xBC,0x07) volatile __bit USETIR;
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__esfr(0xBD) volatile unsigned int URD0IC;
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__esfrbit(0xBD,0x06) volatile __bit URD0IE;
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__esfrbit(0xBD,0x07) volatile __bit URD0IR;
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__esfr(0xBE) volatile unsigned int EPECIC;
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__esfrbit(0xBE,0x06) volatile __bit EPECIE;
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__esfrbit(0xBE,0x07) volatile __bit EPECIR;
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__esfr(0xC0) volatile unsigned int PECCLIC;
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__esfr(0xC2) volatile unsigned int RTC_INTIC;
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__esfr(0xC3) volatile unsigned int XP0IC;
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__esfrbit(0xC3,0x06) volatile __bit XP0IE;
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__esfrbit(0xC3,0x07) volatile __bit XP0IR;
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__esfr(0xC6) volatile unsigned int ABENDIC;
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__esfrbit(0xC6,0x06) volatile __bit ABENDIE;
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__esfrbit(0xC6,0x07) volatile __bit ABENDIR;
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__esfr(0xC7) volatile unsigned int XP1IC;
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__esfrbit(0xC7,0x06) volatile __bit XP1IE;
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__esfrbit(0xC7,0x07) volatile __bit XP1IR;
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__esfr(0xCA) volatile unsigned int ABSTIC;
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__esfrbit(0xCA,0x06) volatile __bit ABSTIE;
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__esfrbit(0xCA,0x07) volatile __bit ABSTIR;
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__esfr(0xCD) volatile unsigned int RES6IC;
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__esfr(0xCE) volatile unsigned int S0TBIC;
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__esfrbit(0xCE,0x06) volatile __bit S0TBIE;
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__esfrbit(0xCE,0x07) volatile __bit S0TBIR;
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__esfr(0xCF) volatile unsigned int XP3IC;
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__esfrbit(0xCF,0x06) volatile __bit XP3IE;
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__esfrbit(0xCF,0x07) volatile __bit XP3IR;
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__esfr(0xE0) volatile unsigned int EXICON;
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__esfr(0xE1) volatile unsigned int ODP2;
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__esfr(0xE3) volatile unsigned int ODP3;
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__esfr(0xE4) volatile unsigned int RTCISNC;
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__esfrbit(0xE4,0x00) volatile __bit T14IE;
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__esfrbit(0xE4,0x01) volatile __bit T14IR;
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__esfrbit(0xE4,0x02) volatile __bit RTC0IE;
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__esfrbit(0xE4,0x03) volatile __bit RTC0IR;
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__esfrbit(0xE4,0x04) volatile __bit RTC1IE;
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__esfrbit(0xE4,0x05) volatile __bit RTC1IR;
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__esfrbit(0xE4,0x06) volatile __bit RTC2IE;
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__esfrbit(0xE4,0x07) volatile __bit RTC2IR;
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__esfrbit(0xE4,0x08) volatile __bit RTC3IE;
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__esfrbit(0xE4,0x09) volatile __bit RTC3IR;
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__esfr(0xE5) volatile unsigned int ODP4;
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__esfr(0xE6) volatile unsigned int RTCCON;
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__esfrbit(0xE6,0x00) volatile __bit RTCR;
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__esfrbit(0xE6,0x01) volatile __bit RTCPRE;
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__esfrbit(0xE6,0x02) volatile __bit T14DEC;
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__esfrbit(0xE6,0x03) volatile __bit T14INC;
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__esfr(0xE7) volatile unsigned int ODP6;
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__esfr(0xE8) volatile unsigned int SYSCON2;
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__esfrbit(0xE8,0x06) volatile __bit RCS;
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__esfrbit(0xE8,0x07) volatile __bit SCS;
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__esfrbit(0xE8,0x0F) volatile __bit CLKLOCK;
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__esfr(0xEA) volatile unsigned int SYSCON3;
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__esfrbit(0xEA,0x00) volatile __bit PERDIS0;
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__esfrbit(0xEA,0x01) volatile __bit PERDIS1;
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__esfrbit(0xEA,0x02) volatile __bit PERDIS2;
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__esfrbit(0xEA,0x03) volatile __bit PERDIS3;
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__esfrbit(0xEA,0x06) volatile __bit PERDIS6;
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__esfrbit(0xEA,0x07) volatile __bit PERDIS7;
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__esfrbit(0xEA,0x08) volatile __bit PERDIS8;
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__esfrbit(0xEA,0x0D) volatile __bit PLLDIS;
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__esfrbit(0xEA,0x0F) volatile __bit GRPDIS;
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__esfr(0xED) volatile unsigned int EXISEL;
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__esfr(0xEE) volatile unsigned int SYSCON1;
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__esfr(0xEF) volatile unsigned int ISNC;
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__esfrbit(0xEF,0x00) volatile __bit RTCT14IR;
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__esfrbit(0xEF,0x01) volatile __bit RTCT14IE;
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__esfrbit(0xEF,0x02) volatile __bit PLLIR;
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__esfrbit(0xEF,0x03) volatile __bit PLLIE;
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__sfr(0x00) volatile unsigned int DPP0;
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__sfr(0x01) volatile unsigned int DPP1;
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__sfr(0x02) volatile unsigned int DPP2;
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__sfr(0x03) volatile unsigned int DPP3;
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__sfr(0x04) volatile unsigned int CSP;
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__sfr(0x05) volatile unsigned int EMUCON;
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__sfr(0x06) volatile unsigned int MDH;
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__sfr(0x07) volatile unsigned int MDL;
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__sfr(0x08) volatile unsigned int CP;
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__sfr(0x09) volatile unsigned int SP;
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__sfr(0x0A) volatile unsigned int STKOV;
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__sfr(0x0B) volatile unsigned int STKUN;
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__sfr(0x0C) volatile unsigned int ADDRSEL1;
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__sfr(0x0D) volatile unsigned int ADDRSEL2;
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__sfr(0x0E) volatile unsigned int ADDRSEL3;
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__sfr(0x0F) volatile unsigned int ADDRSEL4;
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__sfr(0x11) volatile unsigned int ODP0H;
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__sfr(0x12) volatile unsigned int ODP1L;
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__sfr(0x13) volatile unsigned int ODP1H;
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__sfr(0x20) volatile unsigned int T2;
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__sfr(0x21) volatile unsigned int T3;
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__sfr(0x22) volatile unsigned int T4;
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__sfr(0x23) volatile unsigned int T5;
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__sfr(0x24) volatile unsigned int T6;
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__sfr(0x25) volatile unsigned int CAPREL;
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__sfr(0x26) volatile unsigned int GPTCLC;
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__sfrbit(0x26,0x00) volatile __bit GPTDISR;
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__sfrbit(0x26,0x01) volatile __bit GPTDISS;
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__sfrbit(0x26,0x02) volatile __bit GPTSUSPEN;
|
|
__sfrbit(0x26,0x03) volatile __bit GPTEXDISR;
|
|
__sfr(0x30) volatile unsigned int P0LPUDSEL;
|
|
__sfr(0x31) volatile unsigned int P0HPUDSEL;
|
|
__sfr(0x32) volatile unsigned int P0LPUDEN;
|
|
__sfr(0x33) volatile unsigned int P0HPUDEN;
|
|
__sfr(0x34) volatile unsigned int P0LPHEN;
|
|
__sfr(0x35) volatile unsigned int P0HPHEN;
|
|
__sfr(0x36) volatile unsigned int P1LPUDSEL;
|
|
__sfr(0x37) volatile unsigned int P1HPUDSEL;
|
|
__sfr(0x38) volatile unsigned int P1LPUDEN;
|
|
__sfr(0x39) volatile unsigned int P1HPUDEN;
|
|
__sfr(0x3A) volatile unsigned int P1LPHEN;
|
|
__sfr(0x3B) volatile unsigned int P1HPHEN;
|
|
__sfr(0x3C) volatile unsigned int P2PUDSEL;
|
|
__sfr(0x3D) volatile unsigned int P2PUDEN;
|
|
__sfr(0x3E) volatile unsigned int P2PHEN;
|
|
__sfr(0x3F) volatile unsigned int P3PUDSEL;
|
|
__sfr(0x40) volatile unsigned int P3PUDEN;
|
|
__sfr(0x41) volatile unsigned int P3PHEN;
|
|
__sfr(0x42) volatile unsigned int P4PUDSEL;
|
|
__sfr(0x43) volatile unsigned int P4PUDEN;
|
|
__sfr(0x44) volatile unsigned int P4PHEN;
|
|
__sfr(0x48) volatile unsigned int P6PUDSEL;
|
|
__sfr(0x49) volatile unsigned int P6PUDEN;
|
|
__sfr(0x4A) volatile unsigned int P6PHEN;
|
|
__sfr(0x55) volatile unsigned int S0PWM;
|
|
__sfr(0x57) volatile unsigned int WDT;
|
|
__sfr(0x58) volatile unsigned int S0TBUF;
|
|
__sfr(0x59) volatile unsigned int S0RBUF;
|
|
__sfr(0x5A) volatile unsigned int S0BG;
|
|
__sfr(0x5B) volatile unsigned int S0FDV;
|
|
__sfr(0x60) volatile unsigned int PECC0;
|
|
__sfr(0x61) volatile unsigned int PECC1;
|
|
__sfr(0x62) volatile unsigned int PECC2;
|
|
__sfr(0x63) volatile unsigned int PECC3;
|
|
__sfr(0x64) volatile unsigned int PECC4;
|
|
__sfr(0x65) volatile unsigned int PECC5;
|
|
__sfr(0x66) volatile unsigned int PECC6;
|
|
__sfr(0x67) volatile unsigned int PECC7;
|
|
__sfr(0x68) volatile unsigned int PECSN0;
|
|
__sfr(0x69) volatile unsigned int PECSN1;
|
|
__sfr(0x6A) volatile unsigned int PECSN2;
|
|
__sfr(0x6B) volatile unsigned int PECSN3;
|
|
__sfr(0x6C) volatile unsigned int PECSN4;
|
|
__sfr(0x6D) volatile unsigned int PECSN5;
|
|
__sfr(0x6E) volatile unsigned int PECSN6;
|
|
__sfr(0x6F) volatile unsigned int PECSN7;
|
|
__sfr(0x78) volatile unsigned int PECXC0;
|
|
__sfr(0x79) volatile unsigned int PECXC2;
|
|
__sfr(0x7C) volatile unsigned int ABS0CON;
|
|
__sfrbit(0x7C,0x00) volatile __bit ABEN;
|
|
__sfrbit(0x7C,0x01) volatile __bit AUREN;
|
|
__sfrbit(0x7C,0x02) volatile __bit ABSTEN;
|
|
__sfrbit(0x7C,0x03) volatile __bit ABDETEN;
|
|
__sfrbit(0x7C,0x04) volatile __bit FCDETEN;
|
|
__sfrbit(0x7C,0x0A) volatile __bit TXINV;
|
|
__sfrbit(0x7C,0x0B) volatile __bit RXINV;
|
|
__sfr(0x7F) volatile unsigned int ABSTAT;
|
|
__sfrbit(0x7F,0x00) volatile __bit FCSDET;
|
|
__sfrbit(0x7F,0x01) volatile __bit FCCDET;
|
|
__sfrbit(0x7F,0x02) volatile __bit SCSDET;
|
|
__sfrbit(0x7F,0x03) volatile __bit SCCDET;
|
|
__sfrbit(0x7F,0x04) volatile __bit DETWAIT;
|
|
__sfr(0x80) volatile unsigned int P0L;
|
|
__sfr(0x81) volatile unsigned int P0H;
|
|
__sfr(0x82) volatile unsigned int P1L;
|
|
__sfr(0x83) volatile unsigned int P1H;
|
|
__sfr(0x86) volatile unsigned int BUSCON0;
|
|
__sfr(0x87) volatile unsigned int MDC;
|
|
__sfrbit(0x87,0x04) volatile __bit MDRIU;
|
|
__sfr(0x88) volatile unsigned int PSW;
|
|
__sfrbit(0x88,0x05) volatile __bit MULIP;
|
|
__sfrbit(0x88,0x06) volatile __bit USR0;
|
|
__sfrbit(0x88,0x0B) volatile __bit IEN;
|
|
__sfr(0x89) volatile unsigned int SYSCON;
|
|
__sfrbit(0x89,0x00) volatile __bit XPERSHARE;
|
|
__sfrbit(0x89,0x01) volatile __bit VISIBLE;
|
|
__sfrbit(0x89,0x02) volatile __bit XPEN;
|
|
__sfrbit(0x89,0x04) volatile __bit OSCENBL;
|
|
__sfrbit(0x89,0x06) volatile __bit CSCFG;
|
|
__sfrbit(0x89,0x07) volatile __bit WRCFG;
|
|
__sfrbit(0x89,0x08) volatile __bit CLKEN;
|
|
__sfrbit(0x89,0x09) volatile __bit BYTDIS;
|
|
__sfrbit(0x89,0x0A) volatile __bit ROMEN;
|
|
__sfrbit(0x89,0x0B) volatile __bit SGTDIS;
|
|
__sfrbit(0x89,0x0C) volatile __bit ROMS1;
|
|
__sfr(0x8A) volatile unsigned int BUSCON1;
|
|
__sfr(0x8B) volatile unsigned int BUSCON2;
|
|
__sfr(0x8C) volatile unsigned int BUSCON3;
|
|
__sfr(0x8D) volatile unsigned int BUSCON4;
|
|
__sfr(0x8E) volatile unsigned int ZEROS;
|
|
__sfr(0x8F) volatile unsigned int ONES;
|
|
__sfr(0xA0) volatile unsigned int T2CON;
|
|
__sfrbit(0xA0,0x06) volatile __bit T2R;
|
|
__sfrbit(0xA0,0x07) volatile __bit T2UD;
|
|
__sfrbit(0xA0,0x08) volatile __bit T2UDE;
|
|
__sfrbit(0xA0,0x09) volatile __bit T2RC;
|
|
__sfrbit(0xA0,0x0C) volatile __bit T2EDGE;
|
|
__sfrbit(0xA0,0x0D) volatile __bit T2CHDIR;
|
|
__sfrbit(0xA0,0x0E) volatile __bit T2RDIR;
|
|
__sfrbit(0xA0,0x0F) volatile __bit T2IREN;
|
|
__sfr(0xA1) volatile unsigned int T3CON;
|
|
__sfrbit(0xA1,0x06) volatile __bit T3R;
|
|
__sfrbit(0xA1,0x07) volatile __bit T3UD;
|
|
__sfrbit(0xA1,0x08) volatile __bit T3UDE;
|
|
__sfrbit(0xA1,0x09) volatile __bit T3OE;
|
|
__sfrbit(0xA1,0x0A) volatile __bit T3OTL;
|
|
__sfrbit(0xA1,0x0B) volatile __bit FM1;
|
|
__sfrbit(0xA1,0x0C) volatile __bit T3EDGE;
|
|
__sfrbit(0xA1,0x0D) volatile __bit T3CHDIR;
|
|
__sfrbit(0xA1,0x0E) volatile __bit T3RDIR;
|
|
__sfrbit(0xA1,0x0F) volatile __bit T3IREN;
|
|
__sfr(0xA2) volatile unsigned int T4CON;
|
|
__sfrbit(0xA2,0x06) volatile __bit T4R;
|
|
__sfrbit(0xA2,0x07) volatile __bit T4UD;
|
|
__sfrbit(0xA2,0x08) volatile __bit T4UDE;
|
|
__sfrbit(0xA2,0x09) volatile __bit T4RC;
|
|
__sfrbit(0xA2,0x0C) volatile __bit T4EDGE;
|
|
__sfrbit(0xA2,0x0D) volatile __bit T4CHDIR;
|
|
__sfrbit(0xA2,0x0E) volatile __bit T4RDIR;
|
|
__sfrbit(0xA2,0x0F) volatile __bit T4IREN;
|
|
__sfr(0xA3) volatile unsigned int T5CON;
|
|
__sfrbit(0xA3,0x06) volatile __bit T5R;
|
|
__sfrbit(0xA3,0x07) volatile __bit T5UD;
|
|
__sfrbit(0xA3,0x09) volatile __bit T5RC;
|
|
__sfrbit(0xA3,0x0A) volatile __bit CT3;
|
|
__sfrbit(0xA3,0x0B) volatile __bit T5CC;
|
|
__sfrbit(0xA3,0x0E) volatile __bit T5CLR;
|
|
__sfrbit(0xA3,0x0F) volatile __bit T5SC;
|
|
__sfr(0xA4) volatile unsigned int T6CON;
|
|
__sfrbit(0xA4,0x06) volatile __bit T6R;
|
|
__sfrbit(0xA4,0x07) volatile __bit T6UD;
|
|
__sfrbit(0xA4,0x0A) volatile __bit T6OTL;
|
|
__sfrbit(0xA4,0x0B) volatile __bit FM2;
|
|
__sfrbit(0xA4,0x0E) volatile __bit T6CLR;
|
|
__sfrbit(0xA4,0x0F) volatile __bit T6SR;
|
|
__sfr(0xB0) volatile unsigned int T2IC;
|
|
__sfrbit(0xB0,0x06) volatile __bit T2IE;
|
|
__sfrbit(0xB0,0x07) volatile __bit T2IR;
|
|
__sfr(0xB1) volatile unsigned int T3IC;
|
|
__sfrbit(0xB1,0x06) volatile __bit T3IE;
|
|
__sfrbit(0xB1,0x07) volatile __bit T3IR;
|
|
__sfr(0xB2) volatile unsigned int T4IC;
|
|
__sfrbit(0xB2,0x06) volatile __bit T4IE;
|
|
__sfrbit(0xB2,0x07) volatile __bit T4IR;
|
|
__sfr(0xB3) volatile unsigned int T5IC;
|
|
__sfrbit(0xB3,0x06) volatile __bit T5IE;
|
|
__sfrbit(0xB3,0x07) volatile __bit T5IR;
|
|
__sfr(0xB4) volatile unsigned int T6IC;
|
|
__sfrbit(0xB4,0x06) volatile __bit T6IE;
|
|
__sfrbit(0xB4,0x07) volatile __bit T6IR;
|
|
__sfr(0xB5) volatile unsigned int CRIC;
|
|
__sfrbit(0xB5,0x06) volatile __bit CRIE;
|
|
__sfrbit(0xB5,0x07) volatile __bit CRIR;
|
|
__sfr(0xB6) volatile unsigned int S0TIC;
|
|
__sfrbit(0xB6,0x06) volatile __bit S0TIE;
|
|
__sfrbit(0xB6,0x07) volatile __bit S0TIR;
|
|
__sfr(0xB7) volatile unsigned int S0RIC;
|
|
__sfrbit(0xB7,0x06) volatile __bit S0RIE;
|
|
__sfrbit(0xB7,0x07) volatile __bit S0RIR;
|
|
__sfr(0xB8) volatile unsigned int S0EIC;
|
|
__sfrbit(0xB8,0x06) volatile __bit S0EIE;
|
|
__sfrbit(0xB8,0x07) volatile __bit S0EIR;
|
|
__sfr(0xB9) volatile unsigned int SSCTIC;
|
|
__sfrbit(0xB9,0x06) volatile __bit SSCTIE;
|
|
__sfrbit(0xB9,0x07) volatile __bit SSCTIR;
|
|
__sfr(0xBA) volatile unsigned int SSCRIC;
|
|
__sfrbit(0xBA,0x06) volatile __bit SSCRIE;
|
|
__sfrbit(0xBA,0x07) volatile __bit SSCRIR;
|
|
__sfr(0xBB) volatile unsigned int SSCEIC;
|
|
__sfrbit(0xBB,0x06) volatile __bit SSCEIE;
|
|
__sfrbit(0xBB,0x07) volatile __bit SSCEIR;
|
|
__sfr(0xBC) volatile unsigned int URD3IC;
|
|
__sfrbit(0xBC,0x06) volatile __bit URD3IE;
|
|
__sfrbit(0xBC,0x07) volatile __bit URD3IR;
|
|
__sfr(0xBD) volatile unsigned int URD4IC;
|
|
__sfrbit(0xBD,0x06) volatile __bit URD4IE;
|
|
__sfrbit(0xBD,0x07) volatile __bit URD4IR;
|
|
__sfr(0xBE) volatile unsigned int URD5IC;
|
|
__sfrbit(0xBE,0x06) volatile __bit URD5IE;
|
|
__sfrbit(0xBE,0x07) volatile __bit URD5IR;
|
|
__sfr(0xBF) volatile unsigned int URD6IC;
|
|
__sfrbit(0xBF,0x06) volatile __bit URD6IE;
|
|
__sfrbit(0xBF,0x07) volatile __bit URD6IR;
|
|
__sfr(0xC0) volatile unsigned int URD7IC;
|
|
__sfrbit(0xC0,0x06) volatile __bit URD7IE;
|
|
__sfrbit(0xC0,0x07) volatile __bit URD7IR;
|
|
__sfr(0xC1) volatile unsigned int UTD0IC;
|
|
__sfrbit(0xC1,0x06) volatile __bit UTD0IE;
|
|
__sfrbit(0xC1,0x07) volatile __bit UTD0IR;
|
|
__sfr(0xC2) volatile unsigned int UTD1IC;
|
|
__sfrbit(0xC2,0x06) volatile __bit UTD1IE;
|
|
__sfrbit(0xC2,0x07) volatile __bit UTD1IR;
|
|
__sfr(0xC3) volatile unsigned int UTD2IC;
|
|
__sfrbit(0xC3,0x06) volatile __bit UTD2IE;
|
|
__sfrbit(0xC3,0x07) volatile __bit UTD2IR;
|
|
__sfr(0xC4) volatile unsigned int FEI0IC;
|
|
__sfrbit(0xC4,0x06) volatile __bit FEI0IE;
|
|
__sfrbit(0xC4,0x07) volatile __bit FEI0IR;
|
|
__sfr(0xC5) volatile unsigned int FEI1IC;
|
|
__sfrbit(0xC5,0x06) volatile __bit FEI1IE;
|
|
__sfrbit(0xC5,0x07) volatile __bit FEI1IR;
|
|
__sfr(0xCB) volatile unsigned int RES4IC;
|
|
__sfr(0xCE) volatile unsigned int URD2IC;
|
|
__sfrbit(0xCE,0x06) volatile __bit URD2IE;
|
|
__sfrbit(0xCE,0x07) volatile __bit URD2IR;
|
|
__sfr(0xCF) volatile unsigned int URD1IC;
|
|
__sfrbit(0xCF,0x06) volatile __bit URD1IE;
|
|
__sfrbit(0xCF,0x07) volatile __bit URD1IR;
|
|
__sfr(0xD4) volatile unsigned int CLISNC;
|
|
__sfrbit(0xD4,0x00) volatile __bit C0IE;
|
|
__sfrbit(0xD4,0x01) volatile __bit C0IR;
|
|
__sfrbit(0xD4,0x04) volatile __bit C2IE;
|
|
__sfrbit(0xD4,0x05) volatile __bit C2IR;
|
|
__sfrbit(0xD4,0x08) volatile __bit C4IE;
|
|
__sfrbit(0xD4,0x09) volatile __bit C4IR;
|
|
__sfrbit(0xD4,0x0C) volatile __bit C6IR;
|
|
__sfrbit(0xD4,0x0D) volatile __bit C6IE;
|
|
__sfr(0xD5) volatile unsigned int FOCON;
|
|
__sfr(0xD6) volatile unsigned int TFR;
|
|
__sfrbit(0xD6,0x00) volatile __bit ILLBUS;
|
|
__sfrbit(0xD6,0x01) volatile __bit ILLINA;
|
|
__sfrbit(0xD6,0x02) volatile __bit ILLOPA;
|
|
__sfrbit(0xD6,0x03) volatile __bit PRTFLT;
|
|
__sfrbit(0xD6,0x07) volatile __bit UNDOPC;
|
|
__sfrbit(0xD6,0x0D) volatile __bit STKUF;
|
|
__sfrbit(0xD6,0x0E) volatile __bit STKOF;
|
|
__sfrbit(0xD6,0x0F) volatile __bit NMI;
|
|
__sfr(0xD7) volatile unsigned int WDTCON;
|
|
__sfrbit(0xD7,0x00) volatile __bit WDTIN;
|
|
__sfrbit(0xD7,0x01) volatile __bit WDTR;
|
|
__sfrbit(0xD7,0x02) volatile __bit SWR;
|
|
__sfrbit(0xD7,0x03) volatile __bit SHWR;
|
|
__sfrbit(0xD7,0x04) volatile __bit LHWR;
|
|
__sfr(0xD8) volatile unsigned int S0CON;
|
|
__sfrbit(0xD8,0x03) volatile __bit S0STP;
|
|
__sfrbit(0xD8,0x04) volatile __bit S0REN;
|
|
__sfrbit(0xD8,0x05) volatile __bit S0PEN;
|
|
__sfrbit(0xD8,0x06) volatile __bit S0FEN;
|
|
__sfrbit(0xD8,0x07) volatile __bit S0OEN;
|
|
__sfrbit(0xD8,0x08) volatile __bit S0PE;
|
|
__sfrbit(0xD8,0x09) volatile __bit S0FE;
|
|
__sfrbit(0xD8,0x0A) volatile __bit S0OE;
|
|
__sfrbit(0xD8,0x0B) volatile __bit S0FDE;
|
|
__sfrbit(0xD8,0x0C) volatile __bit S0ODD;
|
|
__sfrbit(0xD8,0x0D) volatile __bit S0BRS;
|
|
__sfrbit(0xD8,0x0E) volatile __bit S0LB;
|
|
__sfrbit(0xD8,0x0F) volatile __bit S0R;
|
|
__sfr(0xD9) volatile unsigned int SSCCON;
|
|
__sfrbit(0xD9,0x04) volatile __bit SSCHB;
|
|
__sfrbit(0xD9,0x05) volatile __bit SSCPH;
|
|
__sfrbit(0xD9,0x06) volatile __bit SSCPO;
|
|
__sfrbit(0xD9,0x08) volatile __bit SSCTEN;
|
|
__sfrbit(0xD9,0x08) volatile __bit SSCTE;
|
|
__sfrbit(0xD9,0x09) volatile __bit SSCREN;
|
|
__sfrbit(0xD9,0x09) volatile __bit SSCRE;
|
|
__sfrbit(0xD9,0x0A) volatile __bit SSCPEN;
|
|
__sfrbit(0xD9,0x0A) volatile __bit SSCPE;
|
|
__sfrbit(0xD9,0x0B) volatile __bit SSCBEN;
|
|
__sfrbit(0xD9,0x0B) volatile __bit SSCBE;
|
|
__sfrbit(0xD9,0x0C) volatile __bit SSCAREN;
|
|
__sfrbit(0xD9,0x0C) volatile __bit SSCBSY;
|
|
__sfrbit(0xD9,0x0E) volatile __bit SSCMS;
|
|
__sfrbit(0xD9,0x0F) volatile __bit SSCEN;
|
|
__sfr(0xDD) volatile unsigned int S0CLC;
|
|
__sfrbit(0xDD,0x00) volatile __bit S0DISR;
|
|
__sfrbit(0xDD,0x01) volatile __bit S0DISS;
|
|
__sfrbit(0xDD,0x02) volatile __bit S0SUSPEN;
|
|
__sfrbit(0xDD,0x03) volatile __bit S0EXDISR;
|
|
__sfr(0xE0) volatile unsigned int P2;
|
|
__sfr(0xE1) volatile unsigned int DP2;
|
|
__sfr(0xE2) volatile unsigned int P3;
|
|
__sfr(0xE3) volatile unsigned int DP3;
|
|
__sfr(0xE4) volatile unsigned int P4;
|
|
__sfr(0xE5) volatile unsigned int DP4;
|
|
__sfr(0xE6) volatile unsigned int P6;
|
|
__sfr(0xE7) volatile unsigned int DP6;
|
|
|
|
#endif
|